Teaching in academia

The main objective of this course is to familiarize the student with advanced topics, related to compiler design with focus on backend code generation and optimization. At the end of the course the student should be aware of:
(a) documented techniques for all compiler stages,
(b) analyses, transformations and optimization passes applied to the compilation process,
(c) exploitation of parallelism at all levels,
(d) knowledge of the basic literature (books, published papers) in order to identify sources describing advanced compiler topics, and
(e) practical examples (retargetable compilers and compiler infrastructures) which make use of these techniques.

1. Organization of the typical compiler.


2. Generation of intermediate representation.


3. Code selection.


4. Register allocation.


5. Control and data flow analysis.


6. Machine-independent optimizations.


7. Instruction scheduling for instruction-level parallelism.


8. Machine-dependent optimizations and final code generation.


9. Source-level transformations for enhancing data locality and coarse-level parallelism.


10. Retargetable compilers and compiler development tools.

Course agenda (pdf)

Suggested bibliography on Advanced Compilers (pdf)

Lecture notes and corresponding code packs

• Lecture 01: Organization of the typical compiler (pdf)



• Lecture 02: Intermediate representations (pdf)



• Lecture 03: Code selection (pdf)



• Lecture 04: Register allocation (pdf)



• Lecture 05: Machine-independent optimizations - Control/data flow analysis (pdf)



• Lecture 06: Instruction scheduling and machine-dependent optimizations(pdf)



• Lecture 07: Source-level transformations for enhancing data locality and coarse-level parallelism. (pdf)



• Lecture 08: Final code generation for MIPS32 (pdf)



• Lecture 09: Retargetable compilers and compiler development tools/frameworks (pdf)



• Lecture 10: Overview of compilers and exam preparation (pdf)

• P1: Implementation of code selector (for straight-line or general segments) for a RISC architecture (DLX, MIPS32 or Princeton TOY).
  Suggested tools: OLIVE, IBURG, MonoBURG, JBURG, TOY simulator, TOY assembler (by me, N. Kavvadias "kavi")



• P2: Parameterized linear-scan register allocator
  Suggested tools: Nolimips, DLX simulator written in ArchC (kavi)



• P3: Usage counts-based register allocator
  Suggested tools: same as P2



• P4: Local instruction list scheduler



• P5: Algebraic intermediate representation optimizer written in awk/gawk.



• P6: Peephole optimizer for DLX and/or Princeton TOY
  Suggested tools: copt, gawk

• Spring 2009 exams (pdf)



• Fall 2009 exams (pdf)



• Winter 2010 exams (pdf)



• Fall 2010 exams (pdf)



• Winter 2011 exams (pdf)