Title | ledramp-s3ansk (LED ramp effect) |
Author | Nikolaos Kavvadias (C) 2014 (Modifications/additions) |
Source | User "buserror" (C) 2007 |
Contact | nikos@nkavvadias.com |
Website | http://www.nkavvadias.com |
Release Date | 09 June 2014 |
Version | 1.0.0 |
Rev. history | |
v1.0.0 | 2014-06-09 Initial release for the Spartan-3AN Starter kit board. |
ledramp is a "Knight Rider" style LED ramp effect, which uses two complementary PWM phases for consecutive states. Essentially the first state (PULSE) is a counting state lasting for 0.1 sec. The second state, SHIFT, is where the actual shift (left or right) is applied and the boundary conditions (for the leftmost and rightmost positions) are taken into account.
This version of the design directly uses the 50 MHz clock source available on the Xilinx Spartan-3AN starter kit board.
The design has been adapted from this known original source: http://www.avrfreaks.net/index.php?name=PNphpBB2&file=printview&t=54866&start=40
The ledramp distribution includes the following files:
/ledramp-s3ansk | Top-level directory |
AUTHORS | List of authors. |
COPYING | 3-clause modified BSD license. |
README | This file. |
README.html | HTML version of README. |
README.pdf | PDF version of README. |
ledramp_s3ansk.ucf | User Constraints File for the XC3S700AN-FGG484-4 device. |
ledramp_s3ansk.vhd | The top-level RTL VHDL design file. |
ledramp-syn.sh | Bash shell script for synthesizing the ledramp design with Xilinx ISE. |
impact_s3ansk.bat | Windows Batch file for automatically invoking Xilinx IMPACT in order to download the generated bitstream to the target hardware. |
rst2docs.sh | Bash script for generating the HTML and PDF versions. |
xst.mk | Standard Makefile for command-line usage of ISE. |
The ledramp distribution includes scripts for logic synthesis automation supporting Xilinx ISE. The corresponding synthesis script can be edited in order to specify the following for adapting to the user's setup:
For running the Xilinx ISE synthesis tool, generating FPGA configuration bistream and downloading to the target device, execute the corresponding script from within the ledramp-s3ansk directory:
In order to successfully run the entire process, you should have the target board connected to the host and it should be powered on.
The synthesis procedure invokes several Xilinx ISE command-line tools for logic synthesis as described in the corresponding Makefile, found in the the ledramp-s3ansk directory.
Typically, this process includes the following:
As a result of this process, the ledramp_s3ansk.bit bitstream file is produced.
Then, the shell script invokes the Xilinx IMPACT tool by a Windows batch file, automatically passing a series of commands that are necessary for configuring the target FPGA device: