Downloads related to the ByoRISC ASIP/configurable processor
ByoRISC (Build Your Own RISC) is a customizable and extensible soft core processor family
(referenced in [A8], [B17]). The ByoRISC processors are based on a novel
microarchitecture template developed from scratch with specialized characteristics such as:
For the ByoRISC processors, synthesizable models have been realized in VHDL and cycle-estimate simulators
in ArchC (reference: [B17]).
- support of an extensive list of configuration parameters
- acceleration of the execution of data-intensive loop structures of arbitrary complexity using the
proposed ZOLC (Zero-Overhead Loop Controller) architecture (reference: [A7])
- support of multi-input multi-output application-specific hardware extensions (ASHEs)
- use of an interim pipeline stage of decoding custom instructions, that are supported by a multi-port register file
- zero-overhead cycle execution of multi-input, multi-output instructions
- scalable data forwarding architecture (reference: [A8])
- support of local coprocessors external to the processor pipeline (planning)
- support of multi-cycle custom instructions that incorporate multiple load/store operations
from/to the data memory.
Feel free to download the first version of the "ByoRISC demo" which is based on the ArchC model:
You should run this from a Cygwin/X86 command prompt. Tested on Windows XP.
Partial file listing of the ByoRISC VHDL core project, generated by SLOCCOUNT: