Downloads



  1. A data-dependence graph construction pass for MachSUIF called 'bbpart'). 'bbpart' is an analysis pass built to be used with the SUIF2/MachSUIF2 compiler infrastructure. This pass generates a textual representation for the data dependence graphs of the basic blocks found in all the procedures of a given ANSI C source file. An older version that generates a visual representation in the VCG (Visualization and Compiler Graph) format for each DDG can be found here.


  2. An instruction mix generation pass for MachSUIF called 'instrmix'. 'instrmix' is an analysis pass that generates the SUIFvm instruction mix for a given input source file.
    [UPDATED: 18-July-2004]


  3. 'loopstr' is a tiny pass to generate the natural loop analysis report for the given C procedures.
    [UPDATED: 18-July-2004]


  4. Instruction-accurate ArchC model for the (integer ISA) DLX processor (alpha version): (model)
    [UPDATED: 10-October-2006]


  5. palutils (palette and image utilities) is a collection of handy tools for processing of image files (mainly 8-bit indexed palette bitmaps). Its main focus is on the usage of image files in small-scale embedded systems.
    This is a binary-only release for Windows/Cygwin.
    Link: palutils-demo.zip
    [UPDATED: 28-May-2010].


    6.


  1. SUIFvm instruction set support for the CDIF (Connected Dataflow Idiom Finder) instruction generation tool: (patch)
    [FIXED: 30-March-2006]


  2. A patch for the OLIVE code generator-generator tool, currently only available as part of the SPAM research compiler, which is built on top of SUIF 1. The patch has been tested on Linux Redhat 9.0 with its pre-installed gcc-3.3.2. (patch)
    [FIXED: 29-August-2006]


  3. A patch applying modifications to archc-2.0beta2 (the latest ArchC distribution as of 07-July-2006) so that it can compile with a gcc-2.x-based compiler. It has been (not thoroughly) tested on a Linux Redhat 7.3 with its native gcc-2.96: (patch)


    4.


  1. An implementation of a hardware looping unit (HWLU) in VHDL, originally posted at the Opencores website around April 2004. The HWLU can be used for developing non-programmable engines for multi-dimensional signal processing algorithms that are comprised of fully nested loops. It is accompanied by software tools for generating parts of the VHDL description of the hardware.
    Link:     hwlu.tar.gz
    Opencores link: (HWLU at Opencores)
    [UPDATED: 14-May-2010].


  2. The implementation of "ratpack", a rational arithmetic package written in VHDL. Currently, the "ratpack" package implements the following:
    • the RATIONAL data type and its corresponding constructor (to_rational).

    • int2rat (integer to rational conversion function), and extraction functions (numerator, denominator)

    • basic arithmetic and comparison operators

    • greatest common divisor and mediant computation


    The package is accompanied by two testbenches for operator testing, and computing the Farey series.
    Link: ratpack-0.1.tar.gz
    Opencores link: (ratpack at Opencores)
    [UPDATED: 14-May-2010].


  3. msgmach: LCD (2x16) messaging machine using the Picoblaze 8-bit microprocessor. The messaging machine can be configured for generating a static, side-scrolling ("sliding") or zig-zag scrolling 2-line message.
    A manual is available (in Greek): msgmach.pdf
    4. Files for Xilinx Spartan-3E Starter Kit:
    This exercise was used as part of the "Digital Design Laboratory" as taught in the Electronic Physics M.Sc. curriculum at the Aristotle University of Thessaloniki (A.U.Th.), Greece (2008, 2009).
    [UPDATED: 07-June-2010].

  4. pixview: Hardware-based embedded image viewer written in VHDL for the Spartan-3 starter kit.
    Files for Xilinx Spartan-3 Starter Kit (XC3S200-FT256):
    • Viewing an 8-color mermaid: bitfile
    [UPDATED: 07-June-2010].


  5. mprfgen is a simple-minded multi-port memory generator that you can use for your VHDL designs. It can generate either generic or Xilinx-specific (through component instantiation) multi-port memories. mprfgen has been commercialized by Ajax Compilers (check here soon)
    [UPDATED: 12-May-2013].


  6. All four example designs from an FPGA seminar that took place on June 01, 2011 at the University of Peloponnese, Greece. The seminar illustrated these designs on a Xilinx Spartan-3AN Starter Kit.
    Checkout the recorded video presentation here
    [UPDATED: 15-Jul-2011].


  7. fixed_extensions_pkg is a fixed-point arithmetic package written in VHDL according to the VHDL-2008 update of the standard. It uses VHDL-2008 back-compatible libraries (by David Bishop) that are included in this distribution for the sake of completeness. Link: fixed_extensions.zip
    Opencores link: fixed_extensions at Opencores
    [UPDATED: 05-Sep-2011].


    8.


  1. "kdiv" is a generator of routines for optimized division by an integer constant. It can be used for calculating an integer division with the routines presented in Henry S. Warren's "Hacker's Delight" book. "kdiv" can also be used for emitting a NAC (generic assembly language) or ANSI C implementation of the (signed or unsigned) division. "kdiv" was written these last couple of days.
    "kdiv" is licensed under the Modified BSD License.
    Link:     kdiv.zip
    [UPDATED: 21-May-2011].


  2. interval is a simple implementation of an interval arithmetic API.
    It is (un)licensed under the Public Domain.
    Link: interval.zip
    [UPDATED: 22-Jul-2009].


    3.

  1. 'tcfggen' is an analysis pass built to be used with the SUIF2/MachSUIF2 compiler infrastructure. 'tcfggen' performs (natural) loop analysis in order to map the control flow of a given optimization unit (i.e. a procedure in the input program) to its task control flow graph (TCFG). It is also used to pass the static information for the loops in the given procedure to the subsequent stage(s) in the form of pseudo-instructions. These pseudo-instructions pass information regarding:
    • a) the task transitions,

    • b) the points for task entry and task exit

    • c) the loop parameters (loop bounds and stride) and the basic induction register

    • d) which instructions should be removed for ZOLC execution


    This pass works for the SUIFrm instruction set and has been tested with MachSUIF 2.02.07.15.


  2. 'zolcgen' is a transformation pass operating on SUIFrm assembly files, utilizing the SALTO (System for Assembly Language Transformation and Optimization) API. This pass produces the actual ZOLC initialization code that has to be inserted in a preceding basic block to the loop nest to update the ZOLC storage resources and is typically the first basic block of the targeted procedure. This pass works for the SUIFrm instruction set and has been created for a modified SALTO distribution based on version 1.4.1beta3.


  3. SUIFrm (SUIF real machine) backend for Machine-SUIF 2.02.07.15 (coming soon!)


  4. SUIFrm instruction-based simulation model (with ZOLC extensions) written for ArchC 2.0beta2 (coming soon!)


  5. SUIFrm machine description for SALTO (coming soon!)


  6. Kernel benchmarks for evaluating the ZOLC optimizations (tests)


    7.